Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done. Furthermore, reliability of the optimized G-helix interconnects in a silicon-on-organic substrate assembly has been assessed, which includes the package weight and thermo-mechanical analysis. The pitch size effect on the electrical and mechanical performance of G-Helix interconnects has also been studied.
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e-mail: suresh.sitaraman@me.gatech.edu
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June 2004
Technical Papers
Development of G-Helix Structure as Off-Chip Interconnect
Qi Zhu,
Qi Zhu
Computer-Aided Simulation of Packaging Reliability (CASPaR) Laboratory, The Georgia W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
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Lunyu Ma,
Lunyu Ma
Computer-Aided Simulation of Packaging Reliability (CASPaR) Laboratory, The Georgia W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
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Suresh K. Sitaraman
e-mail: suresh.sitaraman@me.gatech.edu
Suresh K. Sitaraman
Computer-Aided Simulation of Packaging Reliability (CASPaR) Laboratory, The Georgia W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
Search for other works by this author on:
Qi Zhu
Computer-Aided Simulation of Packaging Reliability (CASPaR) Laboratory, The Georgia W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
Lunyu Ma
Computer-Aided Simulation of Packaging Reliability (CASPaR) Laboratory, The Georgia W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
Suresh K. Sitaraman
Computer-Aided Simulation of Packaging Reliability (CASPaR) Laboratory, The Georgia W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
e-mail: suresh.sitaraman@me.gatech.edu
Contributed by the Electronic and Photonic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received April 2003; final revision, January 2004. Associate Editor: Z. Suo.
J. Electron. Packag. Jun 2004, 126(2): 237-246 (10 pages)
Published Online: July 8, 2004
Article history
Received:
April 1, 2003
Revised:
January 1, 2004
Online:
July 8, 2004
Citation
Zhu , Q., Ma , L., and Sitaraman, S. K. (July 8, 2004). "Development of G-Helix Structure as Off-Chip Interconnect ." ASME. J. Electron. Packag. June 2004; 126(2): 237–246. https://doi.org/10.1115/1.1756148
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