Significant thermal gradients and hotspots is a major safety and operational issue in microprocessors, hence accurate real-time monitoring hot spots is a critical need. This thermal monitoring is typically performed using temperature sensors embedded in the chip or processor board. The location of the temperature sensors is primarily determined by the sensor space claim rather than the ideal location for thermal management. This manuscript presents an optimization methodology to determine the most beneficial locations for the temperature sensors inside of the microprocessors, based input from high resolution surface infrared thermography combined with inverse heat transfer solvers to predict hot spot locations. Specifically, the infrared image is used to obtain the temperature map over the processor surface, and subsequently delivers the input to a 3D inverse heat conduction methodology, used to determine the temperature field within the processor. In this paper, simulated thermal maps are utilized to assess the accuracy of the method. The inverse methodology is based in a function specification method combined with a sequential regularization in order to increase accuracy in the results. Together with a number of sensors, the temperature field within the processor is then used to determine the optimal location of the temperature sensors using a genetic algorithm optimization combined with a Kriging interpolation. This combination of methodologies was validated against the Finite Element Analysis of a chip incorporating heaters and temperature sensors. An uncertainty analysis of the inverse methodology and the Kriging interpolation was performed separately to assess the reliability of the procedure.
- Electronic and Photonic Packaging Division
Inverse Conduction Heat Transfer and Kriging Interpolation Applied to Temperature Sensor Location in Microchips
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Gonzalez Cuadrado, D, Marconnet, A, & Paniagua, G. "Inverse Conduction Heat Transfer and Kriging Interpolation Applied to Temperature Sensor Location in Microchips." Proceedings of the ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2017 Conference on Information Storage and Processing Systems. ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. San Francisco, California, USA. August 29–September 1, 2017. V001T01A028. ASME. https://doi.org/10.1115/IPACK2017-74224
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